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| motorola 1 MC145572evk advance information MC145572evk isdn u-interface transceiver evaluation kit this document contains information on a new product. specitcations and information herein are subject to change without notice. order this document by MC145572evk/d motorola semiconductor technical data ? motorola, inc. 1997 rev 2 11/97 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mo t or ola 3 MC145572evk contents paragraph page number title number section 1 introduction 5 1.1 organization of data sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.2 hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.3 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 section 2 hardware reference 12 2.1 u-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.1 line interface circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.2 crystal oscillator (lt mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.3 crystal oscillator (nt mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 s/t-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 status leds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 eia-232 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 bit error analyzer interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5.1 setting up a bit error rate test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.6 MC145572evk test headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.6.1 nt signal header (jp7) pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . 24 2.6.2 lt signal header (jp26) pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . 27 2.7 dip switch functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.7.1 nt side gci parameters dip switch s1 . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.7.2 nt side configuration dip switch s4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.7.3 lt side gci parameters dip switch s1 . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.7.4 lt side configuration dip switch s7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.8 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 section 3 software design description 33 3.1 operating procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.1.1 power on reset and terminal prompt . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.1.2 command line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.1.3 push-button activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1.4 general comments about activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1.5 embedded operations channel, register r6 . . . . . . . . . . . . . . . . . . . . . 34 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 4 contents (continued) paragraph page number title number 3.2 command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2.1 act ? activation/deactivation menu . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.2 brl ? read/write lt u-interface transceiver byte register . . . . . . . . 37 3.2.3 brn ? read/write nt u-interface transceiver byte register . . . . . . . . 38 3.2.4 brs ? read/write s/t-interface transceiver register . . . . . . . . . . . . . 38 3.2.5 brt ? read/write s/t-interface transceiver byte register . . . . . . . . . 39 3.2.6 clr ? clear febe/nebe registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2.7 dea ? activation/deactivation menu . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2.8 dis ? display formatted registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2.9 eoc ? embedded operations channel menu . . . . . . . . . . . . . . . . . . . . . 41 3.2.10 hel ? help menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2.11 lof ? disable lt m4 handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.12 lon ? enable lt m4 handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.13 lpu ? u-interface transceiver analog loop-backs . . . . . . . . . . . . . . . . 44 3.2.14 mm ? modify memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.15 nof ? disable nt1 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.16 non ? enable nt1 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.17 nrl ? read/write lt u-interface transceiver nibble register . . . . . . . 47 3.2.18 nrn ? read/write nt u-interface transceiver nibble register . . . . . . 48 3.2.19 nrs ? read/write s/t-interface transceiver nibble register . . . . . . . . 49 3.2.20 nrt ? read/write s/t-interface transceiver nibble register . . . . . . . . 49 3.2.21 orl ? read/write lt u-interface transceiver byte register . . . . . . . . 50 3.2.22 orn ? read/write nt u-interface transceiver overlay register . . . . . 50 3.2.23 res ? reset s/t- interface transceiver and/or u-interface transceivers 51 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 5 MC145572evk list of figures paragraph page number title number figure 1-1. motorola silicon applications and the MC145572evk . . . . . . . . . . . . . . . . . 7 figure 1-2. MC145572evk functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 1-3. MC145572evk dip switch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 1-4. external connections to the MC145572evk . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2-1. nt line interface schematic and component values . . . . . . . . . . . . . . . . . . 14 figure 2-2. lt line interface schematic and component values . . . . . . . . . . . . . . . . . . 14 figure 2-3. eia-232 interface schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 2-4. access to bit error analyzer interface through j22 and j9 headers . . . . . . 18 figure 2-5. bert gated clock ? 8-bit gated clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 2-6. bert gated clock ? 10-bit gated clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 2-7. bit error rate test set-up nt side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 2-8. loop-back modes for the MC145572evk . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 2-9. power connector pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 6 1 intr oduction 1.1 organization of data sheet this document is composed of three major sections . section 1 introduces the MC145572evk u-interf ace t r ansceiv er ev aluation kit with a br ief descr iption of the e v aluation board and a list of k e y f eatures . also included at the end of section 1 is getting star ted, a shor t tutor ial to help begin w or king with the MC145572evk. section 2 is a br ief descr iption of the hardw are design. section 3 contains the command set descr iptions and e xamples . impor t ant note this user? s man ual ? MC145572evk u-interf ace t r ansceiv er ev aluation kit re vision 2 ? corresponds with MC145572evk pr inted circuit board re vision f with t r mw are v ersion 2.01. if a discrepancy e xists betw een this document and the MC145572 data sheet, the MC145572 data sheet should tak e precedence . 1.2 introduction the MC145572evk u-interf ace t r ansceiv er ev aluation kit pro vides motorola isdn customers a con v enient and eft cient v ehicle f or e v aluation of the MC145572 isdn u-interf ace t r ansceiv er . the approach tak en to demonstr ate the MC145572 u-interf ace t r ansceiv er is to pro vide the user with a fully functional nt1 (netw or k t er mination t ype 1) connected to an l t (line t er mination). an nt1 pro vides tr ansparent 2b+d data tr ansf er betw een the u- and s/t -interf aces . in addition, it pro vides f or netw or k initiated maintenance procedures . the MC145572evk does not ter minate an y isdn call control messages . it also does not ter minate an y maintenance messages receiv ed o v er the s/t -interf ace . the MC145572evk u-interf ace t r ansceiv er ev aluation kit can be used as an nt1 card or as an l t card. the left half of the card is the nt1, while the r ight half of the card is the l t . alter nativ ely , it can be thought of as ha ving both ends of the tw o-wire u-interf ace , e xtending from the customer premise (nt1) to the s witch line card (l t) on a single , stand-alone e v aluation board. figure 1-1 sho ws a typical isdn application using the MC145572 and the mc145574. the kit pro vides the ability to inter activ ely manipulate status registers in the MC145572 u-interf ace t r ansceiv er as w ell as in the mc145574 s/t -interf ace t r ansceiv er with the aid of an e xter nal ter minal. a unique combination of hardw are and softw are f eatures allo ws f or stand-alone or ter minal activ ation of the u-interf ace and as such pro vide an e xcellent platf or m f or nt1 and l t hardw are/softw are de v elopment. the nt1 function can be disab led b y putting dip s witch s4-10 in the nt1 dis position. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 7 MC145572evk figure 1-1. motorola silicon applications and the MC145572evk MC145572 u-interface mc145574 s/t-interface mcu x-frmrs and line i/f nt1/te1 switching scp clock mcmc68sc302 host bus mc145480 codec ta lt lt MC145572 u-interface MC145572 u-interface MC145572 u-interface idl idl bus scp x-frmrs and line i/f equipment nt1 ta x-frmrs and line i/f idl bus scp host bus mc145480 codec mc145574 s/t-interface mc145574 s/t-interface clock scp idl bus mc145480 codec x-frmrs and line i/f host bus clock mcmc68sc302 mcmc68sc302 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 8 1.3 features 1.3.1 general pro vides stand-alone nt1 and l t on single board on-board 68hc05 microcontroller with resident monitor softw are con v enient access to k e y signals nt1 and l t softw are de v elopment platf or m 1.3.2 hardware + 5 v only p o w er supply push-button activ ation of u-interf ace from nt1 stand-alone oper ation f or bit error rate t esting gated data cloc ks pro vided f or bit error rate t esting can be used as a u- or s/t -interf ace t er minal de v elopment t ool on-board 5 ppm l t f requency ref erence eia-232 (v .28) ser ial p or t f or t er minal interf ace 1.3.3 software stand-alone or t er minal oper ation resident fir mw are monitor f or user control of board activ ation and deactiv ation men us embedded oper ations channel microcontroller controlled or a utomatic activ ation/deactiv ation access to all maintenance channels mc68hc05 assemb ly language source code a v ailab le f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 9 MC145572evk 1.4 block diagram f ollo wing is a basic functional b loc k diag r am f or the MC145572evk u-interf ace t r ansceiv er ev aluation kit ( figure 1-2 ). while the board is capab le of activ ating stand-alone , the user ma y decide to use a single ascii ter minal to gain total control of the MC145572evk? s activities . figure 1-2. MC145572evk functional block diagram 1.5 getting started this section is pro vided to f acilitate the user? s introduction to the MC145572evk. t o maximiz e eft ciency when w or king with the MC145572evk, it is recommended that the user become f amiliar with the organization of this document as w ell as the MC145572 u-interf ace t r ansceiv er data sheet. t o identify a star ting point, po w er up the board and activ ate the u-interf ace immediately . the only equipment needed is a 5 v , 250 ma po w er supply , a tw o-wire u-interf ace cab le , and the MC145572evk. note the board shipped from the f actor y w as thoroughly tested and v er it ed to function proper ly pr ior to shipment. if y ou e xper ience an y prob lems or dift culties with the oper ation of the MC145572evk, do not hesitate to call the f actor y or y our local motorola representativ e f or assistance . 1. remo v e the board from its conductiv e en vironment at a static-controlled station. 2. examine the board and its components to mak e cer tain nothing w as damaged dur ing shipment of the board. 3. v er ify that the ics are seated proper ly in the soc k et. 5 ppm clock source reference clock generator MC145572 isdn u-interface transceiver mc145574 isdn s/t-interface transceiver mc68hc705 microcontroller mc145407 gated clock generator gated clock generator MC145572 isdn u-interface transceiver idl idl s/t bertclk nt u-interface lt u-interface ext clk scp rs-232 network termination line termination bertclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 10 4. become f amiliar with the la y out and the v ar ious connectors . locate the po w er connector j19. locate the u-interf ace connectors , j2 (l t u-interf ace side) and j12 (nt u-interf ace side). the dip s witches arr iv e preset from the f actor y (see figure 1-3 ). ref er also to dip switch functions in section 2.8 , f or an e xplanation of the function of each s witch. do not change the position of an y dip s witch until y ou are completely f amiliar with its function. figure 1-3. MC145572evk dip switch configuration s4 s0hi s1hi s2hi gci2048 in1hi in2hi open s0low s1low s2low gci512 in1low in2low closed s3 open mas fsr 8 idl2 par t_mas closed slv fsx=fsr 10 gci ser t_slv resmcu adp nt nt1dis fix te nt1en sohi s1hi s2hi gci2048 in1hi in2hi open s0low s1low s2low gci512 in1low in2low closed s1 mas fsr 8 idl2 par open s2 fsx=fsr rf=fsr slv 10 gci ser closed rfoff fron lt u config lt gci config nt u config nt gci config 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 1 2 3 4 5 6 1 2 3 4 5 6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 11 MC145572evk figure 1-4. external connections to the MC145572evk the board is no w ready f or po w er . 5. connect + 5 v and g round leads to the proper pins on j19. mak e cer tain the integ r ity of the po w er supply being used has been v er it ed to pre v ent an y damage to the MC145572evk. 6. t ur n the po w er supply on. if e v er ything is oka y , the red led d27 near the po w er connector will be illuminated. 7. connect a twisted pair betw een the tw o rj-45 connectors , j12 and j2, at the top of the board. this is the u-loop . 8. depress the reset push-b utton (pb1). this push-b utton is located adjacent to the po w er connector . 9. no w depress the push-b utton mar k ed a ct/dea (pb2) located near the status leds . the y ello w tp/aip status leds on both the nt1 and l t sides should illuminate , f ollo w ed b y both g reen leds , sfs and linkup . this activ ation process should occur within 15 seconds . the nt side def ault activ ation mode is an nt1 so the s/t -interf ace is also tr ying to activ ate b y contin ually tr ansmitting the info1 state on the s/t -interf ace . if the red led ei comes on, indicating an activ ation error has occurred, re-chec k the integ r ity of the connections (i.e ., does the u-loop twisted pair sho w contin uity?). retr y if necessar y . isdn loop simulator j12 j2 j16 5 v/250 ma +5 gnd eia-232c nt lt terminal j19 pb1 pb2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 12 10. if a v ailab le , connect an ascii ter minal to j16 (the db-25 connector on the nt1 side of the board). mak e cer tain the ter minal is set f or 9600 baud, 1 stop bit, and no par ity . if there is no response , re v erse the eia-232 tx and rx signals b y changing the jumpers on jp13. 11. depress the reset push-b uttons and v er ify that the ntl t> prompt has appeared on the ter minal screen. contin ue reading this document to lear n more about the oper ation of the MC145572evk u-interf ace t r ansceiv er ev aluation kit. as alw a ys , please phone the f actor y f or assistance with an y prob lems encountered while getting star ted. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 13 MC145572evk 2 hardw are reference note ref er to the MC145572evk pr inted circuit board and to the MC145572 u-interf ace t r ansceiv er data sheet to supplement this section. please contact the f actor y bef ore committing design to pcb to be guar anteed notit cation of an y impro v ements to the f ollo wing circuitr y . the schematic of the MC145572evk is in appendix a of this man ual. 2.1 u-interface the u-interf ace is implemented with motorola? s single chip MC145572 u-interf ace t r ansceiv er (u10 on the nt1 and u1 on the l t side), pro viding isdn basic rate access capability f or twisted-pair loops with conf or mance to ansi t1.601-1992. f or additional specit cations on designing with and the oper ation of the MC145572, ref er to the MC145572 u-interf ace t r ansceiv er data sheet in addition to this document. 2.1.1 line interface circuitry while the pub lished specit cations f or the u-interf ace t r ansf or mer are intended as such, it is realiz ed that application specit c par ameters (i.e ., pr imar y protection) ma y cause some v ar iation in tr ansf or mer specit cations or pub lished line interf ace v alues . figure 2-1 (representing the nt) and figure 2-2 (representing the l t) sho w the suggested architecture of the line interf ace . the schematic giv es the corresponding v alues used to interf ace the MC145572 to the line using pulse engineer ing pe68628 tr ansf or mer . currently all resistor v alues are accur ate to 1%. secondar y protection on the MC145572evk f or the nt1 side and the l t side are implemented using a simple diode br idge consisting of f our mmbd7000l t1s (d5, d6 on l t side and d18, d19 on nt1 side) to clamp v oltage surges to the po w er supply r ail and to g round. t w o populated tw o surge suppressors (d14, d15, d22 on the nt1 side and d1, d2, d7 on the l t side) are on the line side of the tr ansf or mer . the circuit board has been laid out to allo w resistors to be included in the line side circuitr y to pro vide v oltage spik e and po w er cross protection. these resistors , r17, r21 on the nt side and r1, r6 on the l t side , are populated and jumpers are installed at jp8, jp11 on the nt1 side and jp3, jp20 on the l t side . the jumpers can be inser ted if it is desired to b ypass the line side protection circuitr y . the MC145572evk does not directly address the issue of pr imar y protection. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 14 figure 2-1. nt line interface schematic and component values figure 2-2. lt line interface schematic and component values txp txn rxp rxn c37 MC145572 1 : 1.25 r19 r22 c33 +5 v d18 d19 + 5 v 2 1 jp9 r17 r21 d15 d22 d14 jp11 jp8 j12 rj45 t2 r18 r20 2 1 jp12 2 1 jp7 r23 j13 3 5 6 8 7 4 2 1 j14 txp txn rxp rxn c37 MC145572 1 : 1.25 r3 r7 c8 +5v d5 d6 + 5 v 2 1 jp4 r1 r6 d2 d7 d1 jp5 jp3 j12 rj45 t1 r2 r5 2 1 jp6 2 1 jp2 r8 j3 3 5 6 8 7 4 2 1 jp4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 15 MC145572evk 2.1.2 crystal oscillator (lt mode) in the l t mode , the inter nal phase loc k ed loop (pll) of the MC145572 gener ates a 20.48 mhz cloc k which is phase loc k ed to an 8 khz ref erence cloc k applied at the freqref pin. this assures that the tr ansmitted 2b1q signal is synchroniz ed to the 8 khz frequency ref erence . a single pullab le cr ystal, y1, is all that is required f or the MC145572 oscillator . all other frequency pulling circuitr y is inter nal to the MC145572. it is also possib le to pro vide an e xter nal 8 khz frequency ref erence r ather than using the 8 khz frequency ref erence gener ated on-board from the 5 ppm oscillator , y5. this is accomplished using the rf off -rf on s witch of s2-1 and connecting the e xter nal ref erence to extref of j9. rf off selects the off-board 8 khz frequency ref erence and rf on selects the on-board 8 khz frequency ref erence . see also the e xplanation f or s2-1 and s2-7 in section 2.7.2 . 2.1.3 crystal oscillator (nt mode) the nt -cont gured MC145572 u10, requires only a single pullab le cr ystal, y2, f or its oscillator . all other frequency pulling circuitr y is inter nal to the MC145572. 2.2 s/t-interface the s/t -interf ace resides on the nt1 por tion of the MC145572evk and is implemented using the mc145574 s/t -interf ace t r ansceiv er (u17). the 600 mil 28-pin plastic soic mc145574 conf or ms to both ccitt i.430 and ansi t1.605 specit cations . exter nal line interf ace circuitr y f or s witching betw een nt and te oper ating modes is incor por ated. t w o 8-pin rj-45 telephone jac ks are used at the s/t -interf ace , one cont gured f or the nt mode (j24) of oper ation and one cont gured f or the te mode (j23) of oper ation. the tx pair , pins 4 and 5 on the nt jac k and pins 3 and 6 on the te jac k, are dr iv en b y the txp and txn pins which act as a current limited diff erential v oltage source . the dr iv e resistance (r40, r42) is necessar y to conf or m to the ansi t1.605 pulse mask specit cation. a dual 2.5:1 tur ns r atio tr ansf or mer (t4a:b) is used to couple the tx and rx pairs to the 4-wire interf ace . a high frequency 4-wire common mode chok e tr ansf or mer (t3 f or te and t5 f or nt) pro vides an eff ectiv e means of compliance with emi suppression. the protection diodes (d29a:g, d30a:g mmad1108) pro vide secondar y protection to the mc145574, e v en when it is po w ered do wn, without loading the s/t -interf ace b us . ccitt i.430, etsi ets 300012, and ansi t1.605 specify that the s/t -interf ace v oltage cannot e xceed 1.6 times the nominal v oltage of 750 mv (= 1.2 v). since the mc145574 is designed to oper ate with 2.5:1 tur ns r atio tr ansf or mers , the diode str ucture is required to pro vide protection, while not adv ersely aff ecting the s/t -interf ace when po w er is remo v ed from the de vice . this diode str ucture also protects the circuit against electrostatic discharges (esd) and latch-up . the s/t -interf ace t r ansceiv er implementation on this board can be used in either nt or te mode . pin 4, te/nt(l), of the mc145574 deter mines whether the chip is in nt or te mode of oper ation. when cont gured as a te, pins 9 and 8 are used as dreq uest and dgrant , respectiv ely . the dreq uest pin is used b y an e xter nal controller such as the mc145488 ddlc or the mc68302 imp to request access to the d-channel. when the s/t -interf ace t r ansceiv er gains access to the d-channel time slot on the s/t -interf ace b us , it asser ts dgrant high, inf or ming the e xter nal controller that it can tr ansmit its d-channel data in the ne xt idl d time slot. in the nt mode , pin 6 perf or ms the fix and tfsc functions . fix tells the s/t -interf ace t r ansceiv er to use fix ed or adaptiv e timing reco v er y . tfsc is asser ted when fr ame synchronization has been achie v ed at the s/t -interf ace b us . f or a more complete discussion on d-channel oper ation, please ref er to section 11 of the mc145574/75 s/t -interf ace t r ansceiv er data man ual. with the left side of the board oper ating as an nt1, the mc145574 s/t -interf ace t r ansceiv er is in the nt mode , oper ating as an idl sla v e , and is receiving its cloc k and sync signals from the MC145572 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 16 u-interf ace t r ansceiv er . access to the control registers within the s/t -interf ace t r ansceiv er is gained through the scp interf ace . the registers are displa y ed and changed via resident softw are on the MC145572evk. a complete descr iption of the s/t -interf ace t r ansceiv er registers can be f ound in sections 8, 9, and 10 of the mc145574 s/t -interf ace t r ansceiv er data sheet. 2.3 microcontrollers the MC145572evk is an mc68hc705c8 microcontroller-based system. one microcontroller resides on the board; u15 on the nt1 side which controls both the nt1 and the l t sides . the hardw are reset push-b utton is located ne xt to the po w er supply connection f or the microcontroller . u5 m ust be populated f or the displa y leds to oper ate proper ly . the u-interf ace ma y be activ ated using an ascii ter minal connected to the eia-232 (v .28) por t mar k ed j16 on the nt1 side . the board ma y be activ ated as it stands alone with the push of a b utton. the def ault activ ation mode f or the activ ate/deactiv ate push-b utton, pb2 (located near the front of the board), is as an nt1, with info1 contin ually tr ansmitted on the s/t -interf ace until it receiv es info2. when dip s witch s4-10 is in the nt1dis position, the nt1 functionality is disab led. the l t side initiates activ ation on the u-interf ace . eight status leds (d10, d11, d12, and d13 on l t side and d23, d24, d25, and d26 on the nt1 side) are contin uously updated b y the mc68hc705c8s to pro vide the user with a visual update of the u-interf ace activ ation status . when the MC145572evk is reset, it def aults to nt1 function enab led and automatic handling of m4 maintenance channel on the l t side u-tr ansceiv er . the nt1 function can also be disab led b y enter ing the nof command. the l t maintenance can be disab led b y enter ing the lof command. see section 3.2 f or more inf or mation on lof , lon, nof , and non commands . 2.3.1 status leds t en status leds are pro vided on the MC145572evk to off er the user a quic k visual update to cr itical status par ameters . one red led , d27 on the l t , is located near the po w er connector and is illuminated when + 5 v is applied to the board. one g reen led (d31) mar k ed s/t a ct located near the pb2 (a ct/dea) push b utton, illuminates to indicate that the mc145574 when cont gured as an nt has achie v ed fr ame synchronization. located on both sides of the board are f our leds representing nib b le register 1 (nr1) of each u-interf ace t r ansceiv er . the leds in each bank are each mar k ed with linkup , ei, sfs , and tp/aip . the y map directly to the register contents as sho wn belo w . note the receiv ed data is not tr ansmitted on the idl2 interf ace until linkup is a 1, sfs is a 1, tp/aip is a 1, and either custen (see nr2 in MC145572 u-interf ace t r ansceiv er data sheet) or v er ifact is a 1 (see br9 in MC145572 u-interf ace t r ansceiv er data sheet). b3 b2 b1 b0 nr1 linkup error indication superfr ame sync t r ansparent/ activ ation in prog ress nt (led silkscreen) nt linkup nt ei nt sfs nt tp/aip l t (led silkscreen) l t linkup l t ei l t sfs l t tp/aip f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 17 MC145572evk 2.4 eia-232 interface the MC145572evk pro vides one connector f or comm unication betw een a remote ascii ter minal and the on-board microcontroller ser ial comm unications interf ace (sci). j16 resides on the nt1 side . the connector is an industr y standard db-25 type and br ing, tr ansmit, and receiv e data on- or off-board via motorola? s mc145407 + 5 v eia-232d dr iv er/receiv er . the option is also pro vided to s w ap the t r ansmit and receiv e pins with respect to the ascii ter minal data connector . this appears in the f or m of a set of jumpers located near j16. with the jumpers populated as in case 1 in figure 2-3 , the receiv e signal is present on pin 2 and the tr ansmit signal on pin 3 (rx2 e rx2 and tx3 e tx3). con v ersely in case 2, rx2 e rx2 and tx3 e tx3, the tr ansmit signal is present on pin 2 and the receiv e on pin 3. this option is useful when the user m ust use a cab le in which the tx/rx polar ity at pins 2 and 3 is not kno wn. pin 7 of both j16 is circuit board g round ? all other pins (1, 4 e 6, 8 e 25) are no connects . figure 2-3. eia-232 interface schematic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 rx2 do3tx3 di3 mc145407 1* 2** rx input tx output to mcu receive data in from mcu transmit data out ground data to/fromascii terminal rx3tx2 tx3rx2 j16 * rx3tx2, with jumpers populated on this v er tical column. ** tx3rx2, with jumpers populated on this v er tical column. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 18 2.5 bit error analyzer interface the MC145572evk isdn u-interf ace ev aluation kit pro vides ttl-compatib le gated cloc ks f or the b1, b2, and d time slots to allo w easy connection to a bit error r ate tester . this is accomplished with the use of glue logic. access to these gated cloc k signals is through the 2 x 20 headers (j9 on the l t side and j22 on the nt1 side). figure 2-4 details the connections on both of these headers . the cloc ks are output in either an 8- or 10-bit boundar y mode at the idl cloc k speed. the MC145572evk is shipped from the f actor y cont gured so its gated cloc k outputs are der iv ed from the tsen output, pin 25, gated with the dcl signal from the idl2 interf ace . the 2b+d f or mat is the idl 10-bit fr ame . it can be changed to idl 8-bit fr ame f or mat b y setting br7(b0) to a 1 in the appropr iate u t r ansceiv er . figure 2-4. access to bit error analyzer interface through j22 and j9 headers 1 2 40 39 dreq dgrant ntscpenl stscpenl ltscpenl scpclk scptx ntirql ntidlclk ntidlrx ntidltx ntfsr ntfsx irqlt ntsfar ntsfax ntfref ntfrefo ntgtclk scprx gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd j22 (nt) 1 2 40 39 ltfref extref ltscpenl scpclk scptx ltirql ltidlclk ltidlrx ltidltx ltfsr ltfsx 8 khz ltsfar ltsfax ltfrefo ltgtclk scprx gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd j9 (lt) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 19 MC145572evk the timing diag r ams f or each of these modes are sho wn in figure 2-5 and figure 2-6 . one e xample of a bit error r ate test set-up is e xplained in the f ollo wing section. figure 2-5. bert gated clock ? 8-bit gated clock figure 2-6. bert gated clock ? 10-bit gated clock dout b1 b1 b1 b1 b1 b1 b1 b1 d b2 b2 b2 b2 b2 b2 b2 b2 d b1 b1 b1 b1 b1 b1 b1 b1 d b2 b2 b2 b2 b2 b2 b2 b2 d din fsr dcl ltgtclk ntgtclk (tsen) ntsfar no te: these cloc ks are a v ailab le only when either or7(b5) or or8(b3) is set to 1. the e xample sho wn is f or when the MC145572 is cont gured as f ollo ws: br7(b0)=1, or7(b5)=1, or8(b3)=1. ltsfar " dout b1 b1 b1 b1 b1 b1 b1 b1 d b2 b2 b2 b2 b2 b2 b2 b2 d b1 b1 b1 b1 b1 b1 b1 b1 d b2 b2 b2 b2 b2 b2 b2 b2 d din fsr dcl ltgtclk ntgtclk no te: these cloc ks are a v ailab le only when either or7(b5) or or8(b3) is set to 1. the e xample sho wn is f or when the MC145572 is cont gured as f ollo ws: br7(b0)=0, or7(b5)=1, or8(b3)=1. (tsen) ntsfar ltsfar " f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 20 2.5.1 setting up a bit error rate test bit error r ate testing with tw o diff erent testers has been perf or med. the he wlett p ac kard 1645a data error analyz er and the t elecomm unications t echniques cor por ation fireberd 6000 with lab interf ace adapter ha v e successfully been connected to the MC145572evk. an y bit error test that accepts ttl le v el signals and e xter nal data cloc ks up to 2.56 mhz at ttl le v els ma y be used. the cloc k interf ace suppor ts synchronous cloc k ed data through the use of gated cloc ks r unning at idl r ates of 512 khz, 2.048 mhz, or 2.56 mhz, as deter mined b y register br7(b2) and or7(b4) of the u-interf ace t r ansceiv er . caution the MC145572evk does not suppor t eia-232, rs-422, 50w , or rs-485 interf aces to bit error r ate testers . t o demonstr ate the connection of the MC145572evk u-interf ace t r ansceiv er ev aluation kit to a bit error r ate tester , detailed instr uctions f or one test set-up f ollo ws . example: ex ecuting a 2b+d loop-bac k to the u-interface at the l t end. this e xample sho ws ho w to connect a bit error r ate tester to the MC145572evk. ref er to figure 2-7 f or connection details . the data ? o w f or this e xample occurs as f ollo ws: data is input to the board b y the ber t bo x on ntrxd a t a at the nt1. this data is then input to the MC145572 where it is fr amed, coded, and tr ansmitted o v er the u-interf ace to the l t MC145572, and looped-bac k inter nal to the l t MC145572. the data is then tr ansmitted bac k to the nt MC145572 o v er the u-interf ace , decoded, defr amed, and output from the nt MC145572 on nttxd a t a to the ber t bo x where it is compared to the data or iginally tr ansmitted. 1. mak e the f ollo wing connections to the bit error rate t ester as sho wn in figure 2-7 . a. connect nttxd a t a (bnc j20, d out pin of the nt u-interf ace t r ansceiv er) to the receiv e data input of the ber t bo x. b . connect ntrxd a t a (bnc jp18, d in pin of the nt u-interf ace t r ansceiv er) to the t r ansmit data output of the ber t bo x. c. connect ntclk (bnc j21, gated cloc k output f or the b1+b2+d time slot) to the exter nal t r ansmit and exter nal receiv e cloc k inputs of the ber t bo x. 2. v er ify that the dip s witches are set as in figure 1-3 (v alid f or abo v e-mentioned ber t bo x es). 3. cont gure the bit error r ate tester to tr ansmit data on the r ising edge of the data cloc k and receiv e data on the f alling edge of the data cloc k. 4. using an ascii ter minal connected to j16, activ ate the MC145572evk using the activ ation men u item j . activ ate both u chips , 2b+d loop bac k to u-interf ace at l t end, disab le s/t chip . 5. begin bit error r ate testing when status leds indicate loop is successfully activ ated. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 21 MC145572evk figure 2-7. bit error rate test set-up nt side 2.5.1.1 other loop-back tests. a v ar iety of other loop-bac k modes ma y be implemented. some modes are accessib le through the activ ation men u while others require a w or king kno wledge of the scp registers and are accessed through the command line interf ace of the monitor prog r am. ref er to figure 2-8 and the te xt that f ollo ws f or a descr iption of some of these loop-bac ks . ref er also to the MC145572 data book loop-bac k section. the men u items ref erred to are f or the combined nt/l t mode . j18 nt rxdata j20 nt txdata j21 nt clk 30 w * gnd bit error rate tester external rxclock external txclock receive data in transmit data out * on some cases , this resistor ma y be needed to dampen r inging on cloc k tr ansitions . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 22 figure 2-8. loop-back modes for the MC145572evk a: external har d ware idl loop-bac k on nt1 side . place a jumper betw een bnc j18 ntrxd a t a and bnc j20. then, from the nt/l t activ ation men u, select option i or c . or , from the command line interf ace , disab le the s/t -interf ace t r ansceiv er b y setting nr0(b3) of the mc145574 to a 1. the mc145574 can also be remo v ed from the board. b: idl loop-bac k internal to s/t -interface t ransceiver . this loop-bac k ma y be implemented either from the nt/l t activ ation men u or directly from the command line interf ace . f rom the nt/l t activ ation men u, select option b or h. f rom the command line interf ace , enab le a 2b+d idl loop-bac k in the s/t -interf ace t r ansceiv er b y setting nr6(b3) of the mc145574 to a 1. 5 ppm clock source reference clock generator MC145572 isdn u-interface transceiver mc145574 isdn s/t-interface transceiver mc68hc705 microcontroller mc145407 gated clock generator gated clock generator MC145572 isdn u-interface transceiver idl idl s/t bertclk u-loop ext clk scp rs-232 bertclk a b d e g f h i c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 23 MC145572evk c: other s/t -interface t ransceiver loop-bac ks. a v ar iety of s/t -interf ace and idl loop-bac ks ma y be initiated from the command line interf ace b y setting br6(b7 e b0) in the s/t -interf ace t r ansceiv er . ref er to the mc145574/75 s/t -interf ace data sheet f or more inf or mation. d: idl loop-bac k internal to nt u-interface t ransceiver t o war ds nt1 side . this loop-bac k is also implemented via the command line interf ace b y setting br6(b3) and/or br6(b2) and/or br6(b1) in the nt u-interf ace t r ansceiv er to 1. ref er to the MC145572 u-interf ace t r ansceiv er data sheet f or more inf or mation. e: nt u-interface t ransceiver analog loop-bac ks t o war d nt1 side . f rom command line interf ace , in v ok e lpu n d . see also the loop-bac k modes section in the MC145572 u-interf ace t r ansceiv er data sheet. f: idl loop-bac k internal to u-interface t ransceiver t o war ds u-interface . f rom l t activ ation men u, select option b . f rom the command line interf ace f or either the l t or nt1 side , this loop-bac k is implemented b y setting br6(b7) and/or br6(b6) and/or br6(b5) to 1. g: l t u-interface t ransceiver analog loop-bac ks t o war d l t side . f rom command line interf ace , in v ok e lpu l d . see also the loop-bac k modes section in the MC145572 u-interf ace t r ansceiv er data sheet. h: idl loop-bac k internal to l t u-interface t ransceiver t o war ds connector jp9. this loop-bac k is implemented from the command line interf ace b y setting br6(b3) and/or br6(b2) and/or br6(b1) in the l t side u-interf ace t r ansceiv er to 1. i: external har d ware idl loop-bac k on l t side . place a jumper betw een bnc j7 l trxd a t a and bnc j8 l txd a t a. then from the l t/nt activ ation men u, select option e or i. 2.6 MC145572evk test headers there are f our headers on the MC145572evk with signals of signit cant interest to the user . j22 ? mak es a v ailab le k e y signals on the nt side such as the idl, scp , and bit error r ate test interf aces . j11 and j17 ? mak es a v ailab le k e y test signals from the nt side u-interf ace t r ansceiv er . j1 and j6 ? mak es a v ailab le k e y test signals from the l t side u-interf ace t r ansceiv er . j9 ? mak es a v ailab le k e y signals on the l t side such as the idl, scp , and bit error r ate test interf ace . j1 and j11, 2 x 8 headers , mak e impor tant MC145572 u-interf ace t r ansceiv er test signals easily accessib le . pins 2, 4, 6, and 10 can be decoded to gener ate an e y e patter n. also , an e xter nal cab le can be connected to these headers if it is desired to oper ate the corresponding u-interf ace t r ansceiv er from a par allel data por t. ref er to the MC145572 data sheet f or the e y e data application circuit and timing diag r am. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 24 t ab le 2-1. MC145572 t est header (j11) quic k ref erence , nt side pin no. silkscreen scp mode p arallel p or t mode gci mode 1 irqnt_u irq irq n/c 2 20.48 mhz b ufxt al d4 b ufxt al 3 15.36 mhz 15.36 clk out d3 15.36 clk out 4 txbclk txbclk/fref out /dch in d6 fref out 5 ntscpclk scpclk r/w in2 8 sfsync/sf ax txsfs/sf ax txsfs/sf ax s0 9 ntscprx scprx d0 out1 10 4096 mhz 4.096 clk out d3 4.096 clk out 11 ntscpen scpen cs in1 13 ntscptx scptx d1 out2 14 eyed a t a eyed a t a/dchclk d5 s2 15 + 5 v + 5 v + 5 v + 5 v 16 sysclk/ sf ar sysclk/sf ar/tsen/20.48 mhz sysclk/sf ar/tsen/ 20.48 mhz s1 6 rxbclk rxbclk/dck out d7 clksel 7,12 gnd gnd gnd gnd t ab le 2-2. MC145572 t est header (j1) quic k ref erence , l t side pin no. silkscreen scp mode p arallel p or t mode gci mode 1 irql t_u irq irq n/c 2 20.48 mhz b ufxt al d4 b ufxt al 3 15.36 mhz 15.36 clk out d3 15.36 clk out 4 txbclk txbclk/fref out /dch in d6 fref out 5 l tscpclk scpclk r/w in2 6 rxbclk rxbclk/dck out d7 clksel 8 sfsyn/sf ax txsfs/sf ax txsfs/sf ax s0 9 l tscprx scprx d0 out1 10 4096 mhz 4.096 clk out d3 4.096 clk out 11 l tscpen scpen cs in1 13 scptx scptx d1 out2 14 eyed a t a eyed a t a/dchclk d5 s2 15 + 5 v + 5 v + 5 v + 5 v 16 sysclk/sf ar sysclk/sf ar/tsen/20.48 mhz sysclk/sf ar/tsen/ 20.48 mhz s1 7,12 gnd gnd gnd gnd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 25 MC145572evk note 1 ntidlrx is connected to idl tx pin of the mc145574 s/t -t r ansceiv er . if it is desired f or an e xter nal de vice to receiv e idl data from the mc145574, the signal ntidlrx m ust be connected to the idl receiv e input of the e xter nal de vice . note 2 ntidl tx is connected to idlrx pin of the mc145574 s/t -t r ansceiv er . if it is desired f or an e xter nal de vice to receiv e idl data from the mc145574, the signal ntidl tx m ust be connected to the idl receiv e input of the e xter nal de vice . 2.6.1 nt signal header (jp7) pin descriptions dreq: s/t -interface t ransceiver dreq uest . in the te mode , this signal is used to indicate to the mc145574 that an e xter nal de vice wishes to tr ansmit a la y er 2 fr ame to the nt on the d-channel. ref er to the mc145574 isdn s/t -interf ace t r ansceiv er data sheet. dgrant : s/t -interface t ransceiver dgrant . in the te mode , dgrant oper ates as a d-channel g r ant or clear indication. ref er to the mc145574 isdn s/t -interf ace t r ansceiv er data sheet. ntscpen: scp enab le (nt u-interface t ransceiver scp en). this signal, when held lo w , selects the ser ial control p or t (scp) f or the tr ansf er of control, status , and data inf or mation into and out of the MC145572 u-interf ace t r ansceiv er on the nt1 side (u17). t ab le 2-3. nt1 d a t a signal header (j22) quic k ref erence pin no. silkscreen functional description 2 e 20 even gnd ground 1 dreq s/t -interf ace t r ansceiv er dreq uest 3 dgrant s/t -interf ace t r ansceiv er dgrant 5 ntscpen scp enab le (nt u-interf ace t r ansceiv er) 7 stscpen scp enab le st (st -interf ace t r ansceiv er) 9 l tscpen scp enab le (l t u-interf ace t r ansceiv er) 11 ntscpclk scp cloc k 13 ntscptx scp t r ansmit output from MC145572s 15 scprx scp receiv e input to MC145572s 17 ntirql interr upt request (nt u-interf ace t r ansceiv er) 19 ntidlclk idl cloc k (nt u-interf ace t r ansceiv er) 21 ntidlrx idl receiv e input (nt u-interf ace t r ansceiv er) 23 ntidl tx idl t r ansmit output (nt u-interf ace t r ansceiv er) 25 ntfsr fsr f r ame sync (nt u-interf ace t r ansceiv er) 27 ntfsx fsx f r ame sync (nt u-interf ace t r ansceiv er) 29 stirq interr upt request st (s/t -interf ace t r ansceiv er) 31 ntsf ar receiv e superfr ame alignment (nt u-interf ace t r ansceiv er) 33 ntsf ax t r ansmit superfr ame alignment (nt u-interf ace t r ansceiv er) 35 ntfref synchroniz ed reco v ered cloc k output when in mcu mode of oper ation (nt u-interf ace t r ansceiv er) 37 ntfrefo synchroniz ed reco v ered cloc k output when in gci mode of oper ation (nt u-interf ace t r ansceiv er) 39 ntgtclk dem ultiple x ed time slot cloc k out (nt u-interf ace t r ansceiv er) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 26 stscpen: scp enab le st (s/t -interface t ransceiver scp en). this signal, when held lo w , selects the ser ial control p or t (scp) f or the tr ansf er of control, status , and data inf or mation into and out of the mc145574 s/t -interf ace t r ansceiv er (u17). l tscpen: scp enab le (l t u-interface t ransceiver scp en). this signal, when held lo w , selects the ser ial control p or t (scp) f or the tr ansf er of control, status , and data inf or mation into and out of the MC145572 u-interf ace t r ansceiv er on the l t side (u1). note: there is no corresponding interr upt line from u1 to the microcontroller on the nt side of the board. scpclk: scp cloc k (scp clk). scpclk is used f or controlling the tr ansf er of data into and out of the scp registers of the u17 s/t chip . data is shifted into the de vices from scprx on r ising edges of scpclk. data is shifted out of the de vices on scptx on f alling edges of scpclk. scpclk can be an y frequency up to 4.096 mhz. scptx: scp t ransmit output (scp tx). scptx is used to output control, status , and data inf or mation from the tw o MC145572 u-interf ace t r ansceiv ers and the mc145574 s/t -interf ace t r ansceiv er . scprx: scp receive input (scp rx). scprx is used to input control, status , and data inf or mation to the tw o MC145572 u-interf ace t r ansceiv ers and the mc145574 s/t -interf ace t r ansceiv er . ntirq: interrupt request 1 (nt u-interface t ransceiver irq). the irql1 pin is an activ e lo w open dr ain output used to signal the mcu de vices that an interr upt condition e xists in the nt1 MC145572 u-interf ace t r ansceiv er (u10). on clear ing the interr upt condition, the ntirq pin is retur ned to the high state . ntidlclk: (nt u-interface t ransceiver pin dcl). this pin is an input when the MC145572 is in sla v e mode and an output when the MC145572 is in master mode , as estab lished b y s witch s4-1, mas/sl v . as a timing master in nt mode , this pin pro vides a 512 khz, 2.048 mhz, or a 2.56 mhz cloc k frequency . in gci mode the 2.56 mhz cloc k is not a v ailab le . in gci mode s1-4, gci2048/gci512 selects the cloc k r ate on this pin. in sla v e mode this pin accepts an y cloc k frequency from 512 khz to 8.192 mhz, inclusiv e . ntidlrx: (nt u-interface t ransceiver pin d in ). this pin is the input f or the 2b+d data to be tr ansmitted onto the nt1 u-interf ace . data bits are input on sequential f alling edges of the ntidlclk signal beginning immediately after the fsx pulse occurs . the ntidlrx pin is a don?t care e xcept dur ing v alid b- and d-channel data positions . note that the m and the a bits used in the idl interf ace of the mc145574 s/t -interf ace t r ansceiv er are not used b y the MC145572, and, theref ore , are not receiv ed b y the MC145572. ntidl tx: (nt u-interface t ransceiver pin d out ). this pin is the output f or the 2b+d data receiv ed at the nt1 u-interf ace . data bits are output on r ising edges of the idl clk signal beginning immediately after the fsr pulse occurs . the ntidl tx signal remains in a high impedance state when not outputting 2b+d data or when a v alid fsr signal is missing. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 27 MC145572evk note that the m and the a bits used in the idl interf ace of the mc145574 s/t -interf ace t r ansceiv er are not used b y the MC145572, and, theref ore , are not dr iv en b y the MC145572. ntfsr: (nt u-interface t ransceiver pin fsr). this pin is an input when the MC145572 is cont gured f or sla v e mode and an output when cont gured f or master mode , as estab lished b y s witch s4-1, mas/sl v . in the master mode this output is phase loc k ed to the signal receiv ed at the nt1 u-interf ace . this signal is associated with data output from the d out pin of the MC145572. this signal is also connected to the fsc/fsr pin of the mc145574 s/t -t r ansceiv er . ntfsx: (nt u-interface t ransceiver pin fsx). this pin is an input when the MC145572 is cont gured f or sla v e mode and an output when cont gured f or master mode , as estab lished b y s witch s2-1, mas/sl v . in the master mode this output is phase loc k ed to the signal receiv ed at the nt1 u-interf ace . this signal is associated with data input to the d in pin of the MC145572. stirq: interrupt request t (s/t -interface t ransceiver irq). the stirq pin is an activ e lo w open dr ain output used to signal the mcu de vices that an interr upt condition e xists in the mc145574 s/t -interf ace t r ansceiv er . on clear ing the interr upt condition, the stirq pin is retur ned to the high impedance state . ntsf ax: t ransmit superframe alignment. this pin carr ies a signal that indicates the t rst 2b+d fr ame in a u superfr ame to be tr ansmitted onto the u-interf ace . this signal is not activ e when the nt side MC145572 is cont gured f or full gci mode oper ation. ntsf ar: receive superframe alignment. this pin carr ies a signal that indicates the t rst 2b+d fr ame in a u superfr ame to be receiv ed from the u-interf ace . this signal is not activ e when the nt side MC145572 is cont gured f or full gci mode oper ation. ntfref: sync hr oniz ed cloc k out, mcu mode . when the nt side MC145572 is cont gured f or mcu mode oper ation, s4-4 in idl2 position, this pin pro vides the reco v ered timing cloc k. the frequency of the cloc k at this pin is selected b y prog r amming the nt side MC145572 registers br7(b4) and or7(b4). ntfrefo: sync hr oniz ed cloc k out, gci mode . when the nt side MC145572 is cont gured f or full gci mode oper ation, s4-4 in gci position, this pin pro vides the reco v ered timing cloc k. the frequency of the cloc k is selected betw een 2.048 mhz and 512 khz b y the setting of s3-4, gci2048/gci512. ntclk or ntgtclk: gated idl cloc k output. this pin pro vides a gated cloc k output. the cloc k input of an e xter nal bit error r ate tester should be connected to this signal. gnd: gr ound. negativ e p o w er supply . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 28 2.6.2 lt signal header (jp26) pin descriptions l tfref: u1 frequenc y ref erence . this is the signal at the freqref pin of the l t side MC145572, u1. extref: external ref erence . when dip s witch s2-1, rf on -rf off is in the rf off position, an e xter nal 8 khz frequency ref erence applied to this pin becomes the ref erence cloc k f or the l t side MC145572, u1. l tscpen: scp enab le (l t u-interface t ransceiver scp en). this signal, when held lo w , selects the ser ial control p or t (scp) f or the tr ansf er of control, status , and data inf or mation into and out of the MC145572 u-interf ace t r ansceiv er on the l t side (u1). scpclk: scp cloc k (scp clk). scpclk is used f or controlling the tr ansf er of data into and out of the scp registers of the u chips and the s/t chip . data is shifted into the de vice from scprx on r ising edges of scpclk. data is shifted out of the de vice from scptx on f alling edges of scpclk. scpclk can be an y frequency up to 4.096 mhz. scptx: scp t ransmit output (scp tx). scptx is used to output control, status and data inf or mation from the tw o MC145572 u-interf ace t r ansceiv ers and the mc145574 s/t -interf ace t r ansceiv er . t ab le 2-4. l t signal header (jp9) quic k ref erence pin no. silkscreen functional description 2 e 20 even gnd ground 1 l tfref output f or 8 khz ref erence cloc k 3 extref input f or exter nal 8 khz ref erence cloc k 5 7 9 l tscpen scp enab le (l t u-interf ace t r ansceiv er) 11 scpclk scp cloc k 13 scptx scp t r ansmit output from MC145572s 15 scprx scp receiv e input to MC145572s 17 l tirq interr upt request 2 (l t u-interf ace t r ansceiv er) 19 l tidlclk idl cloc k 2 (l t u-interf ace t r ansceiv er) 21 l tidlrx idl receiv e input (l t u-interf ace t r ansceiv er) 23 l tidl tx idl t r ansmit output (l t u-interf ace t r ansceiv er) 25 l tfsr fsr f r ame sync (l t u-interf ace t r ansceiv er) 27 l tfsx fsx f r ame sync (l t u-interf ace t r ansceiv er) 29 8 khz output f or on-board 8 khz ref erence cloc k 31 l tsf ar receiv e superfr ame alignment (l t u-interf ace t r ansceiv er) 33 l tsf ax t r ansmit superfr ame alignment (l t u-interf ace t r ansceiv er) 35 37 l tfrefo synchroniz ed reco v ered cloc k output when in gci mode of oper ation (l t u-interf ace t r ansceiv er) 39 l tgtclk dem ultiple x ed time slot cloc k out (l t u-interf ace t r ansceiv er) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 29 MC145572evk scprx: scp receive input (scp rx). scprx is used to input control, status , and data inf or mation to the tw o MC145572 u-interf ace t r ansceiv ers and the mc145574 s/t -interf ace t r ansceiv er . l tirq: interrupt request (l t u-interface t ransceiver irq). the l tirq pin is an activ e lo w open dr ain output used to signal the mcu de vices that an interr upt condition e xists in the l t MC145572 u-interf ace t r ansceiv er (u1). on clear ing the interr upt condition, the l tirq pin is retur ned to the high state . l tidlclk: (l t u-interface t ransceiver pin dcl). this pin is an input when the MC145572 is in sla v e mode and an output when the MC145572 is in master mode , as estab lished b y s witch s2-2, mas/sl v . as a timing master in l t mode , this pin pro vides a 512 khz, 2.048 mhz, or 2.56 mhz cloc k frequency . in gci mode , the 2.56 mhz cloc k is not a v ailab le . this choice is prog r ammed in br7 or from the clksel pin of the l t side MC145572. in gci mode s5-4, gci2048/gci512 selects the cloc k r ate on this pin. in sla v e mode , this pin accepts an y cloc k frequency from 512 khz to 8.192 mhz, inclusiv e . l tidlrx: (l t u-interface t ransceiver pin d in ). this pin is the input f or the 2b+d data to be tr ansmitted onto the l t u-interf ace . data bits are input on sequential f alling edges of the l tidlclk signal, beginning immediately after the l tfsx pulse occurs . the l tidlrx pin is a don?t care e xcept dur ing v alid b- and d-channel data positions . l tidl tx: (l t u-interface t ransceiver pin d out ). this pin is the output f or the 2b+d data receiv ed at the l t u-interf ace . data bits are output on r ising edges of the idl clk signal beginning immediately after the l tfsr pulse occurs . the l tidl tx signal remains in a high impedance state when not outputting 2b+d data or when a v alid fs2 signal is missing. l tfsr: (l t u-interface t ransceiver pin fsr). this pin is an input when the MC145572 is cont gured f or sla v e mode and an output when cont gured f or master mode , as estab lished b y s witch s2-2, mas/sl v . in the master mode , this output is phase loc k ed to the 20.480 mhz cloc k of the l t side u chip . this signal is associated with data output from the d out pin of the MC145572. l tfsx: (l t u-interface t ransceiver pin fsx). this pin is an input when the MC145572 is cont gured f or sla v e mode and an output when cont gured f or master mode , as estab lished b y s witch s2-2, mas/sl v . in the master mode , this output is phase loc k ed to the signal receiv ed at the l t u-interf ace . this signal is associated with data input to the d in pin of the MC145572. 8 khz: MC145572evk ref erence cloc k. this pin outputs an 8 khz square w a v e that is gener ated b y the on-board cloc k ref erence . this signal is a v ailab le at all times . l tsf ax: t ransmit superframe alignment. this pin carr ies a signal that indicates the t rst 2b+d fr ame in a u superfr ame to be tr ansmitted onto the u-interf ace . this signal is not activ e when the l t side MC145572 is cont gured f or full gci mode oper ation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 30 l tsf ar: receive superframe alignment. this pin carr ies a signal that indicates the t rst 2b+d fr ame in a u superfr ame to be receiv ed from the u-interf ace . this signal is not activ e when the l t side MC145572 is cont gured f or full gci mode oper ation. when the l t side MC145572 is cont gured f or full gci mode oper ation, s2-5 in gci position, this pin pro vides the reco v ered timing cloc k. the frequency of the cloc k is selected betw een 2.048 mhz and 512 khz b y the setting of s2-4, gci2048/gci512. l tgtclk: gated idl cloc k output. this pin pro vides a gated cloc k output. the cloc k input of an e xter nal bit error r ate tester should be connected to this signal. gnd: gr ound. negativ e p o w er supply . t ab le 2-5. nt and l t side MC145572evk header list header ref erence function j1 access to l t t est signals j2 access to l t 2b1q signal j3 shor t p ositiv e side of the line to ground j4 shor t negativ e side of the line to ground j5 tx/rx headers j6 access to l t tdm signals j7 l t rxd a t a j8 l t txd a t a j9 access to multifunction MC145572 pins j10 l t clk j11 access to multifunction pins j12 access to nt 2b1q signal j13 shor t p ositiv e side of the line to ground j14 shor t negativ e side of the line to ground j15 tx/rx header pins j17 access to nt tdm signals j18 nt rxd a t a j19 p o w er connector j20 nt txd a t a j21 nt clk j22 nt data interf ace signals j23 access to sit 2b1q te j24 access to sit 2b1q nt jp1 l t pwr config jp2 shor t line jp3 shor t r1 jp4 shor t l t sealing current bloc king cap jp5 shor t r6 jp6 t er minate line with 135 w jp7 shor t line jp8 shor t r17 jp9 shor t n7 sealing current bloc king cap jp10 nt pwr config f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 31 MC145572evk 2.7 dip switch functions f our sets of dip s witches are pro vided f or MC145572evk cont gur ation and testing. these s witches are preset at the f actor y . in nor mal oper ation, the MC145572evk is cont gured f or idl oper ation with the mc68hc705 microcontroller comm unicating with the MC145572 u-t r ansceiv ers via the scp interf ace . note when a dip s witch is in the open position, the signal is at a logic 1. when a dip s witch is in the closed position, the signal is at a logic 0. 2.7.1 nt side gci parameters dip switch s1 this dip s witch is used to cont gure the time slot and input pins of the nt side MC145572 when it is cont gured f or gci mode b y setting s4-4 to the gci position. in nor mal oper ation, s4-4 is in the idl position and the settings of this dip s witch do not aff ect oper ation of the MC145572evk. jp11 shor t r21 jp12 t er minate line with 135 w jp13 sw aps tx and rx pins at j16 jp14 def ault t er mination impedance on s/t t r ansmit jp15 def ault t er mination impedance on s/t receiv e t ab le 2-6. nt side gci p arameter s dip switc h s3 dip switc h function description f actor y setting open closed s3-1 s0hi s0lo w prog r am nt side MC145572 gci s0 time slot select pin. s0hi s3-2 s1hi s1lo w prog r am nt side MC145572 gci s1 time slot select pin. s1h1 s3-3 s2hi s2lo w prog r am nt side MC145572 gci s2 time slot select pin. s2hi s3-4 gci2048 gci512 select betw een 2.048 mhz and 512 khz dcl cloc k when nt side MC145572 is in gci mode . gci2048 s3-5 in1hi in1lo w used to select le v el on in1 pin of MC145572 when nt side MC145572 is in gci mode . in2hi s3-6 in2hi in2lo w used to select le v el on in2 pin of MC145572 when nt side MC145572 is in gci mode . in2hi t ab le 2-5. nt and l t side MC145572evk header list (contin ued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 32 2.7.2 nt side configuration dip switch s4 this dip s witch is used to cont gure oper ation of the nt side of the MC145572evk. in par ticular , the MC145572 u-interf ace t r ansceiv er is cont gur ab le f or idl or gci oper ation, master or sla v e timing mode , and p ar allel or ser ial control p or t oper ation. 2.7.3 lt side gci parameters dip switch s1 this dip s witch is used to cont gure the time slot and input pins of the l t side MC145572 when it is cont gured f or gci mode b y setting s2-5 to the gci position. in nor mal oper ation, s2-5 is in the idl2 position and the settings of this dip s witch do not aff ect oper ation of the MC145572evk. t ab le 2-7. nt side cont guration dip switc h s4 dip switc h function description f actor y setting open closed s4-1 mas sl v selects the le v el on the m/s pin to the nt1 u-interf ace t r ansceiv er . mas s4-2 fsr fsr=fsx connects the fsr and fsx pins of the nt side MC145572 when closed. use only in sla v e mode . fsr s4-3 8 10 selects 10- or 8-bit mode gated idl cloc k outputs f or use with a bit error analyz er on the nt1 side when the MC145572 is cont gured f or mcu mode oper ation. 10 s4-4 idl2 gci when open, the MC145572 is cont gured f or mcu oper ation and the time division m ultiple x ed b us interf ace to the MC145572 is in the idl2 mode . when closed, the MC145572 is cont gured f or gci oper ation and all 2b+d and control/status inf or mation is tr ansf erred o v er the gci interf ace . idl2 s4-5 p ar ser selects betw een the ser ial control por t or par allel control por t mode of accessing the nt side MC145572 when s4-4 is in the idl2 mode position. ser s4-6 t_mas t_sl v selects betw een setting the mc145574 as a sla v e or master f or the idl2 b us . clkhi s4-7 resmcu controls the state of the microcontroller reset line . this is an input to the hardw are reset of the mc68hc705c8 and is useful when using another platf or m to control the MC145572evk. when closed, a reset signal is applied to u15. open s4-8 fix adp selects either the adaptiv e or the t x ed timing reco v er y mode f or the s/t -interf ace t r ansceiv er . adp s4-9 te nt selects the oper ating mode of the s/t -interf ace t r ansceiv er ? te mode or nt mode . this signal is tied to the select lines of an analog m ultiple x er that cont gures te/nt(l) (u17-4),sg/dgrant/andout (u17-8), and dreq uest/andin (u17-9) on the mc145574 appropr iately . te s4-10 nt1en nt1dis t ur ns nt1 function on or off . when the nt1 function is off , the user has complete control of all maintenance channel registers via the ter minal interf ace . when open, the nt1 is enab led. when closed, the nt1 is disab led. ntidis t ab le 2-8. l t side gci p arameter s dip switc h s2 dip switc h function description f actor y setting open closed s1-1 s0hi s0lo w prog r am l t side MC145572 gci s0 time slot select pin. s0hi s1-2 s1hi s1lo w prog r am l t side MC145572 gci s0 time slot select pin. s1hi s1-3 s2hi s2lo w prog r am l t side MC145572 gci s0 time slot select pin. s2hi s1-4 gci2048 gci512 select betw een 2.048 mhz and 512 khz dcl cloc k when l t side MC145572 is in gci mode . gci2048 s1-5 in1hi in1lo w used to select le v el on in1 pin of MC145572 when l t side MC145572 is in gci mode . in1hi s1-6 in2hi in2lo w used to select le v el on in2 pin of MC145572 when l t side MC145572 is in gci mode . in2hi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 33 MC145572evk 2.7.4 lt side configuration dip switch s7 this dip s witch is used to cont gure oper ation of the l t side of the MC145572evk. in par ticular , the MC145572 u-interf ace t r ansceiv er is cont gur ab le f or idl or gci oper ation, master or sla v e timing mode , p ar allel or ser ial control p or t oper ation. 2.8 power supply the MC145572evk is a + 5 v only board that pulls appro ximately 250 ma while activ ated and oper ating in the combined nt1/l t mode . it is recommended that a 5 v supply with a 1 a minim um current capability be used. p o w er supply connections are made to the ter minals mar k ed + 5 v and gnd on j19. the ter minal mar k ed al t is reser v ed f or future use . one 1n5339a d28 5 w att z ener regulator diode (5.6 v) protects the MC145572evk from o v er v oltage and re v erse polar ity conditions . figure 2-9. power connector pin assignments t ab le 2-9. l t side cont guration dip switc h s2 dip switc h function description f actor y setting open closed s2-1 rf on rf off selects betw een on-board and off-board 8 khz cloc k ref erence applied to the freqref pin of the l t side MC145572. when open, this s witch selects the on-board 5 ppm ref erence . when closed, the signal at jp26-3 is applied to freqref . see s7-8 descr iption. rf on s2-2 mas sl v selects the le v el on the m/s pin to the nt1 u-interf ace t r ansceiv er . MC145572 is the timing master . mas s2-3 fsr fsx=fsr connects the fsr and fsx pins of the nt side MC145572 when closed. use only in sla v e mode . fsr s2-4 8 10 selects 10- or 8-bit mode gated idl cloc k outputs f or use with a bit error analyz er on the nt1 side when the MC145572 is cont gured f or mcu mode oper ation. 10 s2-5 idl2 gci selects betw een mcu or gci oper ation f or the l t side u-tr ansceiv er . when open, the MC145572 is cont gured f or mcu oper ation and the time division m ultiple x ed b us interf ace to the MC145572 is in the idl2 mode . when closed, the MC145572 is cont gured f or gci oper ation and all 2b+d and control/status inf or mation is tr ansf erred o v er the gci interf ace . idl2 s2-6 rf=fsr when closed, this s witch connects the fsr signal of the l t side MC145572 to the extfref , the e xter nal frequency ref erence input. s2-1 m ust also be in the closed position. rf=fsr s2-7 ? not used. + 5 v gnd alt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 34 3 softw are design description 3.1 operating procedures a resident ter minal prog r am per mits the user to inter act with the MC145572evk. the commands pro vide the f ollo wing functions: a. activ ation with or without loop-bac ks . b . modit cations to and displa ys of registers . c. modit cations to and status of eoc functions . d. deactiv ation options . 3.1.1 power on reset and terminal prompt applying po w er to the MC145572evk causes a po w er on reset to occur which in v ok es the resident ter minal prog r am. 1. when the ter minal is connected to the nt1 side eia-232 connector (j16), the ter minal displa ys the f ollo wing: MC145572evk evaluation card vx.x mc68hc705c8 version ntlt> where: x.x is the softw are re vision n umber . 3.1.2 command line interface after initialization or retur n of control to the monitor , the ter minal displa ys the ntlt> prompt. if an in v alid command is entered, ! invalid command ! is displa y ed on the ter minal. this error message is accompanied b y a bell. all erroneous commands are accompanied b y an appropr iate error message accompanied b y a bell. the MC145572evk w aits f or a command line input from the ter minal. all commands can be entered as lo w er or upper case . when a v alid command has been entered, the command is e x ecuted or a men u is brought up . all men us prompt the user f or appropr iate inputs to select a function or to quit the men u. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 35 MC145572evk note the ter minal interf ace does no t ha v e m ultiple char acter type ahead. 3.1.3 push-button activation one push-b utton is pro vided f or activ ating/deactiv ating the u-interf ace t r ansceiv ers without the necessity of using a ter minal. the activ ate push-b utton (pb2) can be pressed to activ ate/deactiv ate the u-interf ace . pressing the activ ate push-b utton toggles the current activ ation mode . if the u-interf ace t r ansceiv er(s) is not activ ated, pressing the activ ate push-b utton activ ates it. if the u-interf ace t r ansceiv er(s) is activ ated, pressing the activ ate push-b utton deactiv ates it. immediately f ollo wing a reset, the board can be activ ated as an nt1 b y pressing the activ ate push-b utton, and the l t side u-interf ace t r ansceiv er will also attempt to activ ate . if there is no connection to the l t side u-interf ace , the l t u-interf ace t r ansceiv er will not activ ate and an error condition will be displa y ed on the l t side status leds . the same is tr ue if there is no connection to the nt1 side u-interf ace t r ansceiv er , e xcept that the error status is displa y ed on the nt1 side leds . 3.1.4 general comments about activation the monitor softw are contin ually tests f or a u-interf ace t r ansceiv er activ ation in prog ress . if this is detected, the monitor automatically e x ecutes the appropr iate activ ation routine(s). activ ation status is monitored visually from the status leds on each half of the board. when activ ation is in prog ress , the tp/aip led tur ns on. all other leds are off . successful activ ation is indicated b y all leds e xcept f or the ei led being tur ned on. when activ ation f ails , only the ei led tur ns on. 3.1.5 embedded operations channel, register r6 the embedded oper ations channel register is a 12-bit register that appears in the u-interf ace t r ansceiv er nib b le register memor y map , ref erred to as r6 in the MC145572 data sheet. it is wr itten to or read from b y using either the nrl or nrn commands with register 6 specit ed. the monitor alw a ys echoes bac k the register name as r6, not nr6. example ntlt>nrn 6 152 wr ite he x 152 to eoc fr amer r6:152 updated r6 echoed to ter minal ntlt> command line prompt 3.2 command set the f ollo wing pages det ne the command set to be used with the aid of an e xter nal ter minal. a summar y of the MC145572evk softw are command set: a ct : activ ation/deactiv ation men u brl: read/wr ite l t u-interf ace t r ansceiv er byte register brn: read/wr ite nt u-interf ace t r ansceiv er byte register brs: read/wr ite s/t -interf ace t r ansceiv er byte register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 36 br t : read/wr ite s/t -interf ace t r ansceiv er byte register , alter nate f or m clr: clears f ebe/nebe , re-enters br4 and br5 in both l t and nt side u-t r ansceiv ers dea: activ ation/deactiv ation men u, alter nate f or m dis: displa y f or matted registers eoc: embedded oper ations channel men u hel: help men u lof: disab le l t m4 handler lon: enab le l t m4 handler lpu: u-interf ace t r ansceiv er analog loop-bac k mm: modify memor y nof: disab le nt1 non: enab le nt1 nrl: read/wr ite l t u-interf ace t r ansceiv er nib b le register nrn: read/wr ite nt u-interf ace t r ansceiv er nib b le register nrs: read/wr ite s/t -interf ace t r ansceiv er nib b le register nr t : read/wr ite s/t -interf ace t r ansceiv er nib b le register , alter nate f or m orl: read/wr ite l t u-interf ace t r ansceiv er ov er la y register orn: read/wr ite nt u-interf ace t r ansceiv er ov er la y register res: reset s/t and/or u-interf ace t r ansceiv ers 3.2.1 act activation/deactivation menu 3.2.1.1 format. act mo t or ola 37 MC145572evk 3.2.1.2 loop-back options. the activ ate command pro vides t v e diff erent points on the MC145572evk board where loop-bac ks are per mitted when one or both u-interf ace t r ansceiv ers are activ ated. at an y giv en time , only one loop-bac k point can be enab led. this per mits user equipment to be connected to the opposite side of the MC145572evk. f or e xample , if a loop-bac k is selected on the nt1 half of the board, user equipment can be connected to the idl interf ace on the l t side of the MC145572evk. the l t side u-interf ace t r ansceiv er can be activ ated with 2b+d loop-bac k to the u-interf ace . this mode enab les the receiv ed digital data from the u-interf ace to be looped bac k to the l t side u-interf ace t r ansceiv er tr ansmitter , and re-tr ansmitted onto the u-interf ace . the loop-bac k point occurs in the idl interf ace b loc k inter nal to the u-interf ace t r ansceiv er . the l t side u-interf ace t r ansceiv er can also be activ ated without an y loop-bac ks initially enab led. a loop-bac k is then implemented simply b y shor ting bnc j7 rxd a t a to bnc j8 l txd a t a. the nt1 side u-interf ace t r ansceiv er can be activ ated with 2b+d loop-bac k enab led in the s/t -interf ace t r ansceiv er idl interf ace . receiv ed data from the nt1 side u-interf ace t r ansceiv er is tr ansmitted on the idl interf ace to the s/t -interf ace t r ansceiv er where it is looped-bac k to the idl interf ace and re-tr ansmitted b y the nt1 u-interf ace t r ansceiv er to w ards the u-interf ace . the nt1 side u-interf ace t r ansceiv er can be activ ated with the s/t -interf ace t r ansceiv er disab led. this causes the s/t -interf ace t r ansceiv er to three-state its idl interf ace tr ansmitter . this pro vides the nt1 side u-interf ace t r ansceiv ers idl interf ace direct access to the nt1 side idl interf ace . this per mits the user to connect their o wn equipment to the nt1 side idl interf ace without an y possibility of b us contention with the s/t -interf ace t r ansceiv er . the nt1 side u-interf ace t r ansceiv er can also be activ ated without an y loop-bac k. this per mits the nt1 side u-interf ace t r ansceiv er to comm unicate with the s/t -interf ace t r ansceiv er o v er the idl interf ace . a loop-bac k is implemented b y shor ting bnc j18 ntrxd a t a to bnc j20 nttxd a t a. 3.2.1.3 menus. operation with the MC145572evk boar d the a ct command pro vides user access to the full set of activ ation and deactiv ation options . f our men u option g roups are displa y ed on the ter minal. options a through d per mit activ ation of the nt1 side u-interf ace t r ansceiv er independently of the l t side u-interf ace t r ansceiv er . these options w ould typically be used when the nt1 side u-interf ace is connected to an incoming 2b1q line from a centr al oft ce , or to the l t side u-interf ace connector on a second MC145572evk. options e and f per mit activ ation of the l t side u-interf ace t r ansceiv er independently of the nt1 side u-interf ace t r ansceiv er . these options w ould typically be used when the l t side u-interf ace is connected to a separ ate nt1 or to the nt1 side u-interf ace connector on a second MC145572evk. options g through j are used when the l t side and the nt1 side u-interf ace connectors on an MC145572evk are connected together . options k through o are used to deactiv ate the u- and s/t -interf ace t r ansceiv ers in a controlled manner . example 1 ntlt>act f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 38 *** nt\lt activation\deactivation menu *** a..activate nt side as an nt1 b..activate nt side u chip, 2b+d loopback at t chip idl port c..activate nt side u chip, disable t chip d..activate t chip e..activate lt side u chip f..activate lt side u chip, 2b+d loopback to u interface at lt end g..activate both u chips with nt side as an nt1 h..activate both u chips, loopback at t chip idl port i..activate both u chips, disable t chip j..activate both u chips, 2b+d loopback to u interface at lt end, disable t chip k..deactivate lt side u chip l..deactivate nt side u chip m..deactivate t chip n..deactivate nt u chip, t chip o..deactivate all chips mo t or ola 39 MC145572evk note if the r o/w o bit in u-interf ace t r ansceiv er br14 is not set, the data echoed bac k ma y not be the same as the data wr itten to the b yte register . example ntlt>brl 6 1 enab le idl 2b+d loop-bac k tr ansparent br6:01 updated br6 echoed to ter minal ntlt> command line prompt 3.2.3 brn read/write nt u-interface transceiver byte register 3.2.3.1 format. brn mo t or ola MC145572evk 40 the register n umber wr itten to , the specit ed register is updated and the updated register contents are echoed to the ter minal. note bits that are read only/wr ite only bits ma y not necessar ily re? ect the v alue wr itten to them when echoed to the ter minal. example ntlt>brs 6 1 enab le idl b2 loop-bac k non-tr ansparent br6:01 updated br6 echoed to ter minal ntlt>brs 14 aa wr ite he x aa to b yte register 14 br14:aa updated br14 echoed to ter minal ntlt> command line prompt 3.2.5 brt read/write s/t-interface transceiver byte register 3.2.5.1 format. brt mo t or ola 41 MC145572evk = n (nt side u-interf ace t r ansceiv er register set) = l (l t side u-interf ace t r ansceiv er register set) = s (s/t -interf ace t r ansceiv er register set) = t (s/t -interf ace t r ansceiv er register set) = a (all chips) = u (both u-interf ace t r ansceiv ers on-board) note if dis mo t or ola MC145572evk 42 or0:00 or1:04 or2:8 or3:00 or4:04 or5:08 or6:e0 or7:00 or8:00 or9:00 mc145574 s-t chip register contents nr0:0 nr1:b nr2:1 nr3:8 nr4:0 nr5:0 nr6:8 br0:00 br1:00 br2:00 br3:f0 br4:00 br5:00 br6:00 br7:00 br8:c0 br9:00 br10:00 br11:00 br12:00 br13:00 br14:00 br15:4c ntlt> 3.2.9 eoc embedded operations channel menu 3.2.9.1 format. eoc mo t or ola 43 MC145572evk indicates that when the least signit cant bit of the address nib b le is a 0, then eoc data is being tr ansmitted. in ansi ter minology , the address nib b le is ref erred to as the address/message indicator . the softw are on the MC145572evk only responds to eoc addresses of 000 or 111, the broadcast address . the message bit m ust be a 1 and only the se v en ansi det ned eoc commands are suppor ted. these are , in he xadecimal: 50 loop-bac k 2b+d channels at nt1 51 loop-bac k b1 channel at nt1 52 loop-bac k b2 channel at nt1 53 request corr upted crc to be sent from nt1 to l t 54 notify nt1 of incoming corr upt crc from l t ff retur n nt1 to nor mal oper ation 00 hold nt1 in current state f or e xample: with the def ault eoc address nib b le equal to 1, the MC145572evk w ould load 150 into the l t u-interf ace t r ansceiv er nib b le register 6 when men u item c is selected. this w ould be loaded into the l t u-interf ace t r ansceiv er eoc fr amer register , r6, and tr ansmitted to the nt1. the men u per mits a ne w def ault v alue to be selected f or the eoc address nib b le . this is men u item j . the softw are also per mits a custom eoc message to be concatenated with the current def ault eoc address nib b le . this is done b y selecting men u item h. after the custom eoc message has been entered, it is concatenated with the current def ault eoc address nib b le and the 12 bits are loaded into the l t u-interf ace t r ansceiv er eoc fr amer register , r6, and tr ansmitted to the nt1. example 1 MC145572evk: ntlt>eoc eoc commands sent from lt b1 loopback....off request corrupt crc.....off b2 loopback....on notify corrupt crc......off d loopback....off nt1 hold state..........off last eoc sent: fff last eoc received: 151 eoc commands received at nt b1 loopback....off request corrupt crc.....off b2 loopback....on notify corrupt crc......off d loopback....off nt1 hold state..........off f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola MC145572evk 44 last eoc sent: fff last eoc received: 151 **** lt end eoc menu **** a..b1 loopback at nt1 f..return nt1 to normal b..b2 loopback at nt1 g..hold nt1 c..2b+d loopback at nt1 h..send custom eoc message d..nt1 send bad crc i..set default eoc address e..notify nt1 of bad crc j..eoc address = nt1 (0001) mo t or ola 45 MC145572evk mm aa[ dd] r/w memor y adr aa aa = 0 e ff , dd = 0 e ff clr clear all f ebe/nebe registers lon l t m4 handler on lof l t m4 handler off non nt1 enab led nof nt1 disab led u: u chips, l: lt u chip, n: nt u chip, s or t: t chip, a: all < >:required option ntlt> 3.2.11 lof disable lt m4 handler 3.2.11.1 format. lof mo t or ola MC145572evk 46 MC145572evk after in v oking an y of the lpu commands . each u-interf ace t r ansceiv er can be independently put into analog loop-bac k. the echo canceller loop-bac k is an e xter nal analog loop-bac k where data receiv ed on the u-interf ace t r ansceiv er idl rx pin is fr amed up and then tr ansmitted as 2b1q symbols . the 2b1q symbols are receiv ed b y the u-interf ace t r ansceiv er and cancelled b y the echo canceller . only the echo cancellers are enab led dur ing this mode . when the u-interf ace t r ansceiv er is oper ating correctly , br12+br13 should ha v e a lo w v alue . pref er ab ly , br12 should be 00 and br13 should be a lo w v alue . br13 will contin ue to ? uctuate in v alue slightly . br11 should read as 10 or 11. se v er al seconds ma y elapse bef ore the registers reach a steady state and the correct bits are set. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mo t or ola 47 MC145572evk example ntlt>lpu n ntlt>dis n mc145472 u chip register contents (nt) nr0 : 0 nr1 : b nr2 : 0 nr3 : 5 nr4 : 0 nr5 : 0 r6 : 1ff br0 : 77 br1 : 7f br2 : f0 br3 : f9 br4 : ff br5 : c2 br6 : 00 br7 : 04 br8 : 31 br9 : 80 br10 : 00 br11: 47 br12: 03 br13: 64 br14: 00 br15: 46 br15a(r) : 1e br15a(w) : 00 or0 : 00 or1 : 00 or2 : 00 or3 : 00 or4 : 00 or5 : 00 or6 : 00 or7 : 20 or8 : 08 or9 : 00 ntlt> 3.2.14 mm modify memory 3.2.14.1 format. mm aa[ dd] mo t or ola MC145572evk 48 example ntlt>mm 51 read address 51 51:xx unkno wn data read from address 51 ntlt>mm 51 2e wr ite he x 2e to address 51 51:2e echo updated contents to ter minal ntlt> command line prompt 3.2.15 nof disable nt1 function 3.2.15.1 format. nof mo t or ola 49 MC145572evk note bits that are read only/wr ite only ma y not necessar ily re? ect the v alue wr itten to them when echoed to the ter minal. example ntlt>nrl 4 1 enab le m5/m6 channel interr upts nr4:1 updated nr4 echoed to ter minal ntlt>brl 14 40 mak e all registers read/wr ite br14:40 updated br14 echoed to ter minal ntlt>nrl 6 151 wr ite he x 151 to eoc fr amer r6:151 updated r6 echoed to ter minal ntlt> command line prompt 3.2.18 nrn read/write nt u-interface transceiver nibble register 3.2.18.1 format. nrn mo t or ola MC145572evk 50 br14:40 updated br14 echoed to ter minal ntlt>nrn 6 152 wr ite he x 152 to eoc fr amer r6:152 updated r6 echoed to ter minal ntlt> command line prompt 3.2.19 nrs read/write s/t-interface transceiver nibble register 3.2.19.1 format. nrs mo t or ola 51 MC145572evk 3.2.21 orl read/write lt u-interface transceiver byte register 3.2.21.1 format. orl mo t or ola MC145572evk 52 3.2.23 res reset s/t- interface transceiver and/or u-interface transceivers 3.2.23.1 format. res[ device] m o to r ol a re s erv e s the ri g ht to m a k e c hang e s wit h out further n o ti c e t o an y p r odu c ts h e rein. m otorola m ak e s no w arr a nt y , r epre s e n tation or gu a ra n t e e re g a r ding the suitabi l ity o f its p ro d ucts f o r any pa r ticul a r pu r pose, nor d oes m ot o rola a ssu m e any liability a risin g ou t o f t h e ap p lic a tion or u se of a n y p r od u ct or circuit , a nd s p ecific a lly discl a i m s a n y and a l l l i abilit y , i n cl u ding w ithout li m itation co ns e q u e n t i a l or incidental dam a ges. t y p i c al p arameters can and do vary in d i ffe r ent applications and actua l p erfo r mance m ay vary o v e r time . a l l oper a ting pa r a m ete r s , i ncl u ding t y p ic a ls , m ust be valid a t e d f o r each c u sto m er a pplication by custo m e r s tec h nical ex p erts. m oto r ola doe s not c o nvey a n y license u n der its p atent ri g hts n o r the ri g hts of othe r s. m oto r ola p r od u cts a re n o t d e si g ne d , i n t e nd e d , o r auth o rize d f o r u s e as co m ponents i n systems i n tended for su r g i ca l i m plant int o the bod y , or other applicat i o n s intended to suppo r t or s u stain life, o r for any other a pp l icat i on i n w h ich th e f a i l ure o f th e motoro l a pr o duct co u ld c r eate a s i tuat i on w h ere p erson a l i n j ury or d eath may o ccu r . s h o u l d buyer p u rch a se or u se m oto r ola p r od u cts for any such u n int e n d ed o r u n a u t h o r ized a p p licati o n, b u yer sh a ll i n de m n ify a nd h old m o to r ola a n d i ts o f fi c ers, emp l o y ee s , su b s i d i ar i e s , a f f i l i a tes, a n d d i str i b u tor s ha r ml e ss a g a i n st a l l c l a i ms, co s ts, d a mag e s, a n d e xp e ns e s, a n d r e a so n ab l e attorne y fe e s a r i s i ng out of, d i r ectly o r i n d i r e ctl y , a ny c l aim of per s onal injur y or d e at h asso c i ate d w i th s uc h un i ntende d o r u na u thoriz e d use, even i f such c l aim al l ege s that m otoro l a w as ne g lig e nt regard i ng th e d e s i gn or m an u facture of the part. mot o r o la an d are regis t ered tr a demarks of motorola, inc. motorola , inc. is a n equa l opportunity/a f fir m ativ e action e m ploye r . how to reach u s: usa/eur o pe/l o c a t ions no t l i s t ed: motorol a literatur e d i stribution: p .o. box 5405, denve r , colorad o 8 0217. 1-303-675 - 2140 or 1-80 0 -441-2447 ja p a n: m oto r ola jap a n ltd.; sps, t echnica l i n for m atio n cent e r , 3-20 - 1 m i n ami-azabu. m i nato-k u , t okyo 106- 8 573 japan. 81-3-3440 - 3569 asia / p aci f ic: m otorol a se m iconductor s h.k. ltd.; si l ic o n harb o ur centre, 2 dai king street, t a i p o industria l estate , t ao po, n. t ., hong kong . 852- 2 6668334 t echnical inf o r m a t i o n ce n t er: 1-800-5 2 1-6274 home p age: http://motorola.com/se m iconductors/ m c145572evk/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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